1. Field of the Invention
The present invention relates to an improved method and system for functionally testing an integrated circuit.
2. Discussion of the Related Art
In a functional testing, it is checked whether an integrated circuit performs the functions for which it has been designed. Predetermined signals are provided to the inputs of the circuit or of determined circuit blocks and the outputs are read to determine whether they correspond to an expected answer. To test all the possible errors of an integrated circuit, a first approach consists of providing the integrated circuit with all the possible combinations of input states and of checking all the signals provided as a response by the circuit This, however, can take a long time. Error models enable determining the test signals (or test vectors) most adapted to testing a circuit.
A so-called scan test method, applied to a logic block of an integrated circuit, having each of its inputs connected to an output terminal of a flip-flop and each of its outputs connected to an input terminal of a flip-flop, will more specifically be considered herein A scan test system includes means for controlling the writing and the reading of test signals in said flip-flops.
FIG. 1 schematically shows a scan test system associated with an integrated circuit including a combinatorial logic block, or logic block LB. The circuit includes three flip-flops FF1, FF2, and FF3. Input and output terminals D1 and Q1 of flip-flop FF1 are respectively coupled to an output terminal O1 and to an input terminal I1 of block LB. Similarly, the input and output terminals D2, Q2, and D3, Q3 of flip-flops FF2 and FF3 are respectively coupled to output and input terminals O2, I2, and O3, I3 of block LB. Clock terminals CK1, CK2, and CK3 of flip-flops FF1, FF2, and FF3 receive a same clock signal CLK. Flip-flops FF1, FF2, and FF3, as well as logic block LB, form the functional part of the circuit The circuit test system includes multiplexers Mi (where i ranges between 1 and 3), each associated with the flip-flop FFi of the same rank. The output terminal of each multiplexer Mi is connected to the input Di of same r A fast input terminal of each multiplexer Mi is connected to output terminal Oi of block LB. A control terminal of each multiplexer Mi receives a signal SC. The second input terminal of multiplexer M1 is connected to an input terminal SI of the circuit The second input terminals of multiplexers M2 and M3 are respectively connected to output terminals Q1 and Q2 of flip-flops FF1 and FF2. Terminal Q3 of flip-flop FF3 is connected to an output terminal SO of the circuit.
Outside of test periods, signal SC is inactive and multiplexers Mi are controlled so that outputs Oi of the logic block are connected to inputs Di of flip-flops FFi. When signal SC is active, multiplexers Mi are controlled so that flip-flops FFi form a FIFO-type test register rated by clock signal CLK.
FIG. 2 schematically illustrates the operation of the test system of FIG. 1.
In a first step, signal SC is maintained active so that flip-flops FF1, FF2, and FF3 form the test register. Test data TD3, TD2, and TD1 are successively presented to SI at the rate of pulses of clock signal CLK, at times t1, t2, and t3. At time t3, data TD3, TD2, and TD1 are respectively stored in flip-flops FF3, FF2, and FF1. Data TD3′, TD2′, and TD1′ are then presented on output terminals O3, O2, and O1 of logic block LB.
In a second step, after time t3, signal SC is made inactive so that the multiplexers connect output terminals O3, O2, and O1 of the logic block to input terminals D3, D2, and D1 of the flip-flops. At the next pulse of signal CLK, at a time t4, data TD3′, TD2′, and TD1′ are stored in flip-flops D3, D2, and D1. Signal SC is made active again after time t4.
In a third step, starting from the reactivation of signal SC, data TD3′, TD2′, and TD1′ are shifted in the test register at the rate of pulses of clock signal CLK, at times t5 and t6, and are successively provided to terminal SO. During this shift, a new test vector TD6, TD5, TD4 is input in the register. Data TD3′, TD2′, and TD1′ provided to terminal SO are compared with their expected values, generally logic “0s” or “1s”.
These three steps are repeated many times as test vectors have been provided. The analysis of the data provided by the logic block as a response to the test data, collected during each third step, enables determining whether the circuit includes defective elements. A defective element is, according to the error model conventionally used, an element having an output abnormally fixed to 0 or to 1. Such a test system operates satisfactorily if the logic block includes no element capable of disturbing the operation of the test register, or to disturb the propagation of the signals in the logic block. Even if such disturbing elements exist, existing test systems are adapted to inhibiting them.
FIG. 3 schematically shows a test system for an integrated circuit similar to the circuit shown in FIG. 1, in which three types of disturbing elements have been inserted.
A first disturbing element is an AND gate 2, a first input of which receives clock signal CLK, the second input of which is coupled to a clock enable signal EN1 generated in block LB, and the output of which is connected to terminal CK2. Gate 2 is capable of disturbing the sequencing of the test register, if for example data provided to block LB cause the inactivation of signal EN1 and the blocking of flip-flop FF2. The flip-flop assembly can then no longer operate as a shift register during the test. To solve this type of problem and make the circuit testable, a solution provided in prior art consists of adding an OR gate 4, the output final of which is connected to the second input terminal of AND gate 2, a first input terminal of which receives clock enable signal EN1, and a second input terminal of which receives a control signal TEST. When the circuit is not tested, signal TEST is made inactive, gate 4 transmits signal EN1 to gate 2 without influencing the circuit operation. When the circuit is tested, signal TEST is activated, the output of gate 4 remains activated whatever signal EN1, and gate 2 is no longer capable of disturbing the sequencing of the test register.
A second disturbing element is an element 5 which provides a reset signal RS to a reset terminal RST of flip-flop FF3 via an output terminal O5. Element 5 is capable of disturbing the sequencing of the test register, if for example test data provided to block LB cause the activation of signal RS and the resetting of flip-flop FF3. To make the circuit testable, a multiplexer 6 having an output terminal connected to terminal RST of flip-flop FF3 and a first input terminal connected to output O5 of the logic block has been added. A second input of multiplexer 6 receives a controllable signal TRST, for example permanently inactive. When the circuit is not tested, signal TEST is made inactive and multiplexer 6 transmits signal RS without influencing the circuit operator. When the circuit is tested, signal TEST is made active and multiplexer 6 permanently provides controllable signal TRST to terminal RST of flip-flop FF3. Thereby, block 5 is not capable of disturbing the sequencing of the test register.
A third disturbing element is a switch 8 capable of disturbing the propagation of a signal OD provided by block LB to output terminal O1. Terminal O1 is connected to a signal storage element 9 and switch 8 receives a signal EN2 generated by block LB. Switch 8 is capable of disturbing the circuit testing, especially during a second step of the testing, if test data provided to block LB cause the inactivation of signal EN2 and the opening of switch 8. Storage element 9 then provides the last value of the signal that it has received. The logic circuit is no longer combinatorial and it is no longer testable by scanning. To make the circuit testable, an OR gate 10, an output of which is connected to control switch 8, a first input terminal of which receives enable signal EN2, and a second input terminal of which receives signal TEST has been added. When the circuit is not tested, signal TEST is made inactive and gate 10 transmits signal EN2 to switch 8 without influencing the circuit operation. When the circuit is tested, signal TEST is made active, the output of gate 10 remains activated whatever signal EN2, and switch 8 remains closed and is no longer capable of disturbing the circuit testing.
When signal TEST is made active, the operation of the test system shown in FIG. 3 is similar to the operation illustrated in FIG. 2 of the test system of FIG. 1.
A disadvantage of the test system of FIG. 3 is that it does not enable testing the proper operation of elements 2, 5, and 8 inhibited by inhibiting means 4, 6, and 10 of the test system. The testing of elements 2, 5, and 8 must then be performed by means of specific test vectors, without using the test system. As the size and complexity of integrated circuits increases, the number of disturbing elements becomes significant and it becomes difficult to provide all the necessary specific test vectors.